This invention relates, in general, to semiconductor devices and more particularly to a novel gate injected, electrically alterable, floating gate memory device.
In U.S. Pat. No. 4,162,504 which was filed on Dec. 27, 1977 and issued on July 24, 1979 and in a pending application Ser. No. 065,436 filed on Aug. 10, 1979, both assigned to the same assignee as the subject application, there is described various floating gate memory embodiments of metal-oxide-semiconductor (MOS) devices wherein current carriers are injected into the floating gate from the controlled gate as distinguished from the prior art which injects current carriers into the floating gate from the substrate. Both references are directed towards structures which produce non-volatile, electrically programmable Gate Injected MOS devices (GIMOS) and while the various embodiments detailed therein operate quite satisfactorily, it was found that the write/erase voltages of the GIMOS devices were only slightly (although significantly) lower than that of a Floating Gate Avalanche MOS (FAMOS) device while the charge retention and charge endurance characteristics of the GIMOS devices were vastly superior to those of the FAMOS devices. Aside from the difficulties detailed in the aforementioned references associated with the erasure of a single "word" in a FAMOS device, other serious defects become apparent. For example, there is a marked tendency towards zener breakdown at the drain-substrate junction particularly at high voltages. Further, since charge is placed on the floating gate by means of electrons or holes flowing through the thin layer of gate oxide material, it has been found that after a relatively few charge and discharge (write/erase) cycles the FAMOS device undergoes a radical change in threshold voltage which may require its replacement. It has been theorized that during transit of charge through the thin gate oxide layer, the layer is sufficiently disrupted to markedly change the threshold voltage.
Another memory device presently in the prior art is U.S. Pat. No. 4,104,675 which issued to D. J. DeMaria on Aug. 1, 1978. This last mentioned reference describes a structure wherein a relatively thick layer of thermally grown SiO.sub.2 is formed over a silicon body having drain and source wells formed therein. A number of graded layers of Semi-Insulating Polycrystalline Silicon (SIPOS) is then formed on the thick SiO.sub.2 layer with each layer of SIPOS having an increasing excess of silicon content. Finally, the SIPOS layer is provided with a layer of aluminum (Al). It is stated that the charge (holes or electrons) will be trapped in the SiO.sub.2 layer about 50 Angstroms from the Si-SiO.sub.2 interface. However, this trapping phenomenon, as is obvious to those skilled in the art, is strongly dependent on how the thermally grown SiO.sub.2 is processed. Practically speaking, even the slightest variation in production techniques, from run-to-run, will produce a slightly different quality of SiO.sub.2. Hence, since trapping is so highly dependent on the processing techniques, threshold voltages as well as the density of the trapped charges and their location cannot be expected to be consistent from one production run to the next. Thus, the character of the SiO.sub.2 will determine the depth to which the greatest density of trapped charges will be located. In any event, all charge injected will not be trapped in the thick, thermally grown SiO.sub.2 but instead some charge will completely traverse the SiO.sub.2 layer to be trapped in the underlying silicon layer. It is thus seen that neither the charge density nor the charge level will be consistent in this prior art device.